The NAND flash memory is a nonvolatile semiconductor memory which can be electrically erased and written online. The NAND flash memory has many advantages, such as high erasing and writing speed, low power consumption, large capacity and low cost. The NAND flash memory may be applied in many electronic products, such as MP3, MP4, cell phone, digital camera and video camera. The data is written into or read from the NAND flash memory via the NAND flash controller. The data transmitted to the NAND flash memory includes address and command data and message data. In the prior art, the address and command data and message data are sent to the NAND flash memory via an internal data transmission channel.
FIG. 1 is a structure diagram showing an existing NAND flash controller. The NAND flash controller includes a bus timing interface 11, an internal data transmission channel 12, a command data decoder 13 and a flash timing generator 14. The bus timing interface 11 directly sends the data transmitted from the system bus to the flash timing generator 14 via the internal data transmission channel 12. The flash timing generator 14 converts the system bus timing into a NAND flash memory timing and sends the data to the NAND flash memory.
The data includes address and command data and message data. When the command data is transmitted in the internal data transmission channel 12, the command data needs to be resolved by the command data decoder 13. After the command data is converted into an actual command, the actual command is sent to the NAND flash memory.
The NAND flash controller is an asynchronous low-speed device. The transmission speed of the NAND flash controller is low and normally less than 40 MHz. However, the transmission speed of the system bus is high and normally up to 133 MHz. During the data transmission, the data from the system bus is always in a waiting state. Moreover, when the command data is transmitted in the internal data transmission channel 12, a conversion operation needs to be performed on the command data by the command data decoder 13. The conversion operation further delays the transmission speed of the NAND FLASH controller and the data transmission efficiency of the NAND flash controller is lowered.
Due to different manufacturers of the NAND flash memory, the value of the command data may be different. Even the manufacturer is the same, different type of NAND flash memories may have different values of the command data. The command data decoder 13 in the NAND flash controller converts different command data in the NAND flash memory from different manufacturers according to the command conversion information stored in the command data decoder 13. However, the command conversion information which may be stored in the command data decoder 13 is finite and it is difficult to include all of the command conversion information in connection with all manufacturers. Moreover, because the NAND flash memory develops rapidly, the solution in which the command data is stored through hardware can not be compatible with the command data which will be put forward in the feature. Thus, the compatibility of the NAND flash controller is limited and it is not flexible to implement the data exchange between the NAND flash controller and different NAND flash memories.
Currently, each page of the NAND flash memory includes two regions: the data region and the redundant region. The data region is adapted to store the data information and the redundant region is adapted to store the file system information and the check bit of the error correcting code. With the data of 2K bytes as an example, the format of the data stored in the NAND flash memory is as shown in table 1.
TABLE 1512 byte512 byte512 byte512 byte16 byte16 byte16 byte16 byteMessageMessageMessageMessageFileCheckFileCheckFileCheckFileCheckdata 0data 1data 2data 3systembit 0systembit 1systembit 2systembit 3information 0information 1information 2information3
As shown in table 1, the data region of the data page includes the anterior 2048 bytes and the redundant region of the data page includes the posterior 64 bytes. A BCH codeword includes the message data of 512 bytes and the file system information and check bit of 16 bytes corresponding to the message data of 512 bytes.
When the data is to be written into the NAND flash memory, after the first message data of 512 bytes is written, the address pointer jumps to the fifth column in table 1, thus, the file system information and the check bit corresponding to the first message data of 512 bytes is written. Then, the address pointer jumps to the second column in table 1 and the next message data of 512 is written, then, the address pointer jumps to the sixth column in table 1 so as to write the file system information and the check bit corresponding to the next message data of 512 bytes. In this cycle, the data is written into the storage page of the NAND flash memory. When the data is to be read from the NAND flash memory, the address pointer needs to be adjusted continuously so as to read the data from corresponding position.
In the above procedure in which the data is written into or read from the NAND flash memory, a special instruction and address need to be sent so as to control the address pointer to jump for writing data into or reading data from a corresponding position. Therefore, the complexity of reading data from or writing data into the NAND flash memory is increased and the data transmission efficiency is lowered.